Dynamic random access memory (DRAM) is a type of volatile random access memory used in modern computing systems. DRAM technology advantages include higher density and lower cost, since a storage cell requires only one transistor and a capacitor per bit of storage. Static or non-volatile memories, on the other hand, require more devices.
Double-data-rate (DDR) memory is a kind of synchronous DRAM, which responds to control inputs on specific edges of the clock and is therefore synchronized with the computer's system bus. DDR memory can transfer data on the rising and the falling edges of a clock—referred to as double-pumping. One benefit of DDR memory is the ability to transfer data at eight times the data rate of the DRAM memory cells it contains, thus enabling higher bus rates and higher peak rates than earlier memory technologies. However, there is no corresponding reduction in latency, which may be proportionally higher.
For example, in third generation DDR memory (DDR3) a read column address strobe (CAS) may be issued to the DRAM only after a write-to-read period (tWTR) following the completion of a write transfer from the memory controller on an external bus. Then the memory controller must wait for a CAS latency period (tCL) to receive the read data transfer from the DRAM on the external bus. During this turnaround time period (tWTR+tCL) between the end of a writing data and the beginning of reading data on the external bus/interface, internal DRAM write and read transfers are taking place on an internal DRAM bus. Thus the memory controller must wait for the duration of this turnaround time period for a read data transfer, the duration of which may be critical to system performance.
In order to reduce the turnaround time, internal busses and/or data buffers may be replicated so as to eliminate internal conflicts, but such replications result in increases in area and in cost, which in turn, reduce some of the primary advantages of using DRAM technology (i.e. higher density and lower cost).
To date, more efficient techniques for reducing such turnaround time periods have not been fully explored.